Because GTKWave is designed to handle many signals at once, it has three signal searching modes (Regular Expressions, Hierarchy, and Tree) as well as the ability to display data in many different formats such as signed or unsigned decimal, hexadecimal, octal, ASCII, real number, binary, and even analog. Source code annotation is currently possible only for Verilog; a parser currently does not exist to do this for VHDL or SystemC.
There has been some confusion on the development history of GTKWave. The 1.x branch was developed by the original author up until he took a break from the project. At the point where the original author suspended working on it, a 2.0 branch was created and developed for a time as a component of the asynchronous logic tool Balsa being developed by Advanced Processor Technologies Group (APT). But APT eventually abandoned its work on the 2.0 branch, and the changes that they made were orphaned. The original author later resumed work on GTKWave roughly where he left off, at the end of the 1.3 series. In order to prevent confusion with the now abandoned 2.0 branch, the main development has been renamed from 1.3.x to 3.x, and this is where development continues to this day. Users of Balsa must still use the 2.0 branch as the functionality of that branch has not been ported back into the main development path
The viewer supports both post-mortem viewing of VCD files and interactive viewing of VCD data, known as partial loading. With this feature, the output of a simulator can be written to a named pipe and then fed to the viewer through a shared memory proxy. The user can then navigate the dump as it is being written to the pipe and watch the simulation output in real time. Coupled with the GtkPlug mechanism, this allows for the viewer to be integrated with other simulators in order to provide an interactive environment all in one window. Tcl scripting and callback capability allow for remote control by other applications. Starting with the 3.3 series, Bluespec Workstation is able to start GTKWave from the workstation, send signals from the workstation to the waveform viewer, and display mnemonics for enumerated types, structured buses, etc.
Supported File Formats
GHW - format generated by the open source VHDL simulator GHDL which supports native VHDL datatypes.
LXT, LXT2 - interLaced eXtensible Trace, natively generated by Verilog simulators such as Icarus Verilog and VeriWell. LXT2 files are accessed via a well-defined reader and writer API. LXT support is limited to a write-only API, so conversion from LXT back into another format requires the use of the GTKWave tracedump export function.
VZT - Verilog/VHDL Zipped Trace, features a very high compression ratio and support for multiprocessor acceleration during reads. For user convenience, access to VZT files is provided through reader and writer API calls. The reader and writer API closely mimic that of LXT/LXT2.
FST - Fast Simulation Trace, next generation simulation dump format with fast reader/writer performance and excellent compression ratio provided by dynamic data deduplication. The writer API more-or-less maps to the VCD file format. The reader API is similar to that of LXT2. FST can be generated directly by the simulators CVC and Icarus Verilog.
FSDB - Fast Signal Database, requires that the executable fsdbdebug from Debussy is found in the shell search path during ./configure. It is used to extract information from the FSDB file on the fly.
Download the sourcecode tar.gz file.